«Systems and Means of Informatics»
Scientific journal
Volume 21, Issue 1, 2011

Content | About  Authors

Abstract and Keywords.

DEVELOPMENT OF COMPUTER-AIDED STATISTICAL SCIENTIFIC SUPPORT FOR HIGH PRECISION AND WITH HIGH AVAILABILITY SYSTEMS.

• I.N.Sinitsyn  IPI RAN, sinitsin@dol.ru
• E.R.Korepanov  IPI RAN, ekorepanov@ipiran.ru
• V.V.Belousov  IPI RAN, vbelousov@ipiran.ru
• V.S.Shorgin  IPI RAN, vshorgin@ipiran.ru
• I.V.Makarenkova  IPI RAN, imakarenkova@ipiran.ru
• T.D.Konashenkova  IPI RAN, tkonashenkova@ipiran.ru
• E.S.Agafonov  IPI RAN, eagafonov@ipiran.ru
• N.N.Semendyaev  IPI RAN, nsemendyaev@ipiran.ru

Abstract:  Methodological foundations of computer-aided support of statistical research based on canonical expansions of random functions are considered. Examples of software tools for high precision and astronomentric systems and bank systems with high availability are presented.

Keywords:  circular (angular) random variables, functions, processes and systems; computer-aided statistical scientific support systems; high precision systems; systems with high availability; statistical dynamics of Earth rotation

EVOLUTION OF MODERN MICROPROCESSORS ARCHITECTURE.

• S. Zamkovetc   IPI RAN, SZamkovetc@ipiran.ru
• V. Zakharov   IPI RAN, VZakharov@ipiran.ru
• V. Krasovsky   INEUM, Krasovsky v@ineum.ru

Abstract:  Preconditions of the first microprocessors with CISC architecture development are considered. Its shortages, partially connected with its redundancy, are discussed. The development of RISC architecture microprocessors as an alternative to CISC is considered. It is pointed that both architectures apply dynamical control of instructions execution. Static method of control is used in VLIW architectures, which features are also described. In such case, the main part of the control process is performed by compilers.

Keywords:  microprocessor; architecture; CISC; RISC; VLIW; pipeline; out-of-order

MODEL OF PARALLEL ROUND OF WORK TREES.

• V. Kozmidiady  IPI RAN, v.kozmidiady@gmail.com

Abstract:  A mechanism is considered, summarizing MapReduce that is aimed at Massive parallel processing. Consideration is based on the fact that a common task forms the tree of works, difficult works are divided into parts up to the obtaining of simple works that can be executed in parallel. The mathematical model of work tree execution is proposed. The methods of round of such trees and their influence on common time of execution are considered.

Keywords:  MapReduce; massive parallel processing; round of trees; work tree

FAULT TOLERANCE METHOD OF CACHE COHERENCE MAINTENANCE SYSTEM.

• B. Z. Shmeilin  IPI RAN, shmeilin@mail.ru

Abstract:  The increase fault tolerance method of cache coherence maintenance system with snooping protocol is presented. In the suggested method, requests, states, and signals in protocol realization scheme are coded. For fault tolerance achievement in coherence maintenance logic, the code, correcting single and detecting double error, is applied to coded requests, states, and signal lines. An improvement of fault tolerance method of cache coherence maintenance systems with snooping protocol is considered. Codes for requests, states, and signals in protocol realization scheme are developed. Codes for correction single and detecting double errors in requests, states, and signals lines are presented.

Keywords:  cache coherence; snooping protocols; fault tolerance; error-correcting code

SELF-TIMED ANALYSIS OF SOME TYPES OF DIGITAL DEVICE.

• Y. Stepchenkov  IPI RAN, YStepchenkov@ipiran.ru
• Yu. Diachenko  IPI RAN, YDiachenko@ipiran.ru
• Yu. Rogdestvenski  IPI RAN, YRogdest@ipiran.ru
• N.Morozov  IPI RAN, NMorozov@ipiran.ru

Abstract:  An approach to verification of digital circuits for self-timed by means of software tools that implement the event-based method is presented. It is shown that relatively simple means provide a total-lot test fullness of the self-timed analysis for shift registers as well as for memory registers. A technique for debugging an arbitrary circuit during its self-timed analysis is suggested. The necessity of a hierarchical approach to self-timed analysis of a complicated circuit is grounded.

Keywords:  self-timed circuits; self-timed analysis; test completeness of the analysis; closing; hierarchical analysis

ON SELF-TIMED PROPERTY OF DIGITAL ELECTRONIC CIRCUITS.

• L. Plekhanov  IPI RAN, LPlekhanov@ipiran.ru

Abstract: The self-timed concept (both independence from delays and diagnostic properties) from the practical point of view and its connection with classical definition of independence from delays are discussed. It is shown that only independence from the delays is not enough for self-timed property. Practical outcomes of the theoretical statements in the area of self-timed circuits development are presented. A link with recent state standard on reliability is shown.

Keywords:  self-timed circuits; independent fromdelays circuits; self-timed analysis

PARTICULARITIES OF TAXONOMIC SELF-TIMED CIRCUITS ANALYSIS.

• Y. Rogdestvensky  IPI RAN, YRogdest@ipiran.ru
• N.Morozov  IPI RAN, NMorozov@ipiran.ru
• A. Rogdestvenskene  IPI RAN, ARogdest@ipiran.ru

Abstract:  The article deals with a method of asynchronous circuits analysis examining their functionality independence on gate's delays. Suggested method theoretically is based on transition diagrams (in global models) with their following equivalent transforming into the event models. Developed algorithms of analysis have a strict fundamentality of global models method but do not require a complete inspection of accessible states of the circuit. As a result, the complexity of the problem has changed from exponential to the polynomial one. Taxonomic analysis clarifies the properties of the investigated schemes, presents a detailed diagnostics and determines possible reasons of violations.

Keywords:  self-timed circuits; event analysis; computer-aided design

EXECUTING SYSTEM FOR CODE SYNTHESIZED ON THE BASE OF SPECIFICATIONS ON THE LANGUAGE CELL.

• O. Bondarenko  IPI RAN, olga@ipi.ac.ru
• K. Volovich  IPI RAN, kv@ipi.ac.ru
• V. Kondrashe  IPI RAN, vd@ipi.ac.ru

Abstract:  Issues of the program code generation that provides the functioning of the hierarchical state machines developed on the language Cell are considered. The concept of `runtime system' as a program code included by compiler of the language Cell into procedural code in order to provide the functioning of the main algorithm of the hierarchical state machines is described. The serialization of the procedural code which is executed by compiler Cell during its synthesis suggests a possibility of the effective functioning of the state machine without an operating system. It assigns to executing system a task to manage all the resources used by the hierarchical state machine.

Keywords:  language Cell; cell; executing system; resource management; serialization; hierarchical state machine; software synthesis; telecommunication protocol

ALGORITHMS FOR THE COMPILER OF THE LANGUAGE CELL.

• O. Bondarenko  IPI RAN, olga@ipi.ac.ru
• K. Volovich  IPI RAN, kv@ipi.ac.ru
• V. Kondrashe  IPI RAN, vd@ipi.ac.ru

Abstract:  The main features of the compiler of the language Cell, developed for the program- ming of hierarchical state machines used in the specification including the behavior of telecommunication protocols are considered. The algorithms of its syntactic and semantic analyzers are presented. Also, the aspects of the synthesis of executable code of the hierarchical state machines in a procedural language C serialized for sequential execution of commands are considered.

Keywords:  language Cell; hierarchical state machine; executing serialization; context of hierarchy; software synthesis; telecommunication protocol

SPECIFIC FEATURES OF THE TIME-MEASURING DEVICES IMPLEMENTATION IN VIRTUAL MACHINES.

• V. Yu. Egorov  Department of Computer Science, Penza State University, vec@mail.ru
• M. A. Shpadyrev  Penza State University, lordm@nm.ru

Abstract: Time-measuring devices included in the personal computer as well as the problems of developing similar devices in virtual machines and methods of their solution are described.

Keywords:  time-measuring devices; virtual machine; hypervisor; guest operating system

DIRECT MEMORY ACCESS REQUEST SERVICING IN HARD DISK CONTROLLERS OF VIRTUAL MACHINES.

• M. A. Shpadyrev  Penza State University, lordm@nm.ru

Abstract:  The peculiarities of a direct memory access request servicing in physical and virtual hard disk controllers are considered. The existing methods of such requests servicing in virtual machines are described. A new method based on a multithread data processing is introduced.

Keywords:  hard disk controller; direct memory access; virtual machine; virtual device; hypervisor