Systems and Means of Informatics

2025, Volume 35, Issue 1, pp 149-169

PROPERTIES AND OPTIMIZATION OF SELF-TIMED CIRCUITS

V. N. Zakharov
Yu. A. Stepchenkov
Yu. G. Diachenko
N. V. Morozov
L. P. Plekhanov
D. Yu. Stepchenkov

Abstract

The article is devoted to the brief overview of the development trends and achievements of self-timed (ST) circuits. Due to redundant data coding and two-phase discipline, ST circuits have a number of advantages over synchronous counterparts. They operate reliably with any cell delays, detect any constant faults, and have an extremely wide performance range in terms of supply voltage and ambient temperature. Practical development of ST units with varying complexity has proven the effectiveness of ST solutions, especially in highly reliable and fault-tolerant applications. The article presents the comparative test results of synchronous and ST circuit test chips and the performance and fault tolerance estimates for ST circuits of varying complexity. Group indication of multibit ST circuits increases their performance by 40% due to a slight increase (less than 3%) in hardware complexity. The developed design methods of protection against soft errors improve the natural immunity of ST circuits to adverse effects and ensure a level of fault tolerance of ST circuits several times higher than that of the synchronous counterparts.

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