Systems and Means of Informatics
2023, Volume 33, Issue 2, pp 4-12
MULTIPLEXED SELF-TIMED PIPELINE
- Yu. A. Stepchenkov
- Yu. G. Diachenko
- D. Yu. Stepchenkov
- D. Yu. Diachenko
- G. A. Orlov
Abstract
The article considers the problem of correct practical implementation of a self-timed pipeline with multiplexing of actively operating stages taking into account the circuitry limitations imposed by the technology used. Complementing two parallel branches with a self-timed marker FIFO (First- Input-First-Output) reduces the average latency of the pipeline and ensures its operation is self-timed. With sufficient FIFO capacity, successive data portions can be processed simultaneously by different pipeline's branches. The circuitry solutions of the multiplexed pipeline's individual units guarantee pipeline practical feasibility in any complementary metal-oxide-semiconductor process at domestic semiconductor factories.
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[+] About this article
Title
MULTIPLEXED SELF-TIMED PIPELINE
Journal
Systems and Means of Informatics
Volume 33, Issue 2, pp 4-12
Cover Date
2023-06-10
DOI
10.14357/08696527230201
Print ISSN
0869-6527
Publisher
Institute of Informatics Problems, Russian Academy of Sciences
Additional Links
Key words
self-timed circuit; pipeline; multiplexing; latency; performance
Authors
Yu. A. Stepchenkov , Yu. G. Diachenko , D. Yu. Stepchenkov , D. Yu. Diachenko , and G. A. Orlov
Author Affiliations
Federal Research Center "Computer Science and Control", Russian Academy of Sciences, 44-2 Vavilov Str., Moscow 119333, Russian Federation
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