Systems and Means of Informatics
2020, Volume 30, Issue 2, pp 4-10
SELF-TIMED COMBINATIONAL CIRCUIT TOLERANCE TO SHORT-TERM SOFT ERRORS
- Yu. A. Stepchenkov
- Yu. G. Diachenko
- Yu. V. Rogdestvenski
- N. V. Morozov
- D. Yu. Stepchenkov
- D. Yu. Diachenko
Abstract
The paper considers self-timed (ST) complementary metal-oxide- semiconductor (CMOS) combinational circuit tolerance to short-term soft errors caused by the external sources or internal noises that do not lead to semiconductor structure destruction. The paper discusses the consequences of physical causes impact, leading to soft errors in a chip manufactured by the 65-nanometer and below CMOS process. It introduces soft error classification in CMOS ST combinational circuits depending on their appearance time and the type of failure. Self-timed circuits have a higher degree of resistance to short-term soft errors than their synchronous counterparts due to the two-phase operation discipline, request-acknowledge interaction, and dual-rail information signal coding. The paper proposes circuitry and layout methods ensuring the lowering of CMOS ST combinational circuit sensitivity to soft errors due to the guaranteed absence of the bipolar influence of the soft error source on the cells forming dual-rail signals and on their wires in the circuit layout.
[+] References (6)
- Kishinevsky, M., A. Kondratyev, A. Taubin, and V. Varshavsky. 1994. Concurrent hardware: The theory and practice of self-timed design. J. Wiley & Sons. 368 p.
- Stepchenkov, Yu. A., Yu. G. Diachenko, and G. A. Gorelkin. 2011. Samosinkhronnye skhemy - budushchee mikroelektroniki [Self-timed circuits are microelectronics future]. Voprosy radioelektroniki [Issues of Radioelectronics] 2:153-184.
- Stepchenkov,Y. A., A.N. Kamenskih, Y. G. Diachenko, Y. V. Rogdestvenski, and D. Y. Diachenko. 2019. Fault-tolerance of self-timed circuits. 10th Conference (International) on Dependable Systems, Services, and Technologies Proceedings. IEEE. 41-44. doi: 10.1109/DESSERT.2019.8770047.
- Taubin, A., A. Kondratyev, J. Cortadella, and L. Lavagno. 1999. Behavioral transformations to increase noise immunity in asynchronous specifications. 5th Symposium (International) on Advanced Research in Asynchronous Circuits and Systems Proceedings. IEEE. 36-47. doi: 10.1109/ASYNC.1999.761521.
- Eaton,P., J. Benedetto, D. Mavis, K. Avery, M. Sibley, M. Gadlage, andT. Turflinger. 2004. Single event transient pulse width measurements using a variable temporal latch technique. IEEE T. Nucl. Sci. 51(6):3365-3368. doi: 10.1109/TNS.2004.840020.
- Danilov, I. A., M. S. Gorbunov, A. I. Shnaider, A. O. Balbekov, Y. B. Rogatkin, and
S. G. Bobkov. 2016. DICE-based Muller C-elements for soft error tolerant asynchronous ICs. 16th European Conference on Radiation and Its Effects on Components and Systems. IEEE. Art. No. F4. doi: 10.1109/RADECS.2016.8093145.
[+] About this article
Title
SELF-TIMED COMBINATIONAL CIRCUIT TOLERANCE TO SHORT-TERM SOFT ERRORS
Journal
Systems and Means of Informatics
Volume 30, Issue 2, pp 4-10
Cover Date
2020-06-30
DOI
10.14357/08696527200201
Print ISSN
0869-6527
Publisher
Institute of Informatics Problems, Russian Academy of Sciences
Additional Links
Key words
self-timed circuit; soft error; fault tolerance; CMOS; working phase; spacer; layout
Authors
Yu. A. Stepchenkov , Yu. G. Diachenko , Yu. V. Rogdestvenski , N. V. Morozov , D. Yu. Stepchenkov , and D. Yu. Diachenko
Author Affiliations
Institute of Informatics Problems, Federal Research Center "Computer Science
and Control", Russian Academy of Sciences, 44-2 Vavilov Str., Moscow 119333, Russian Federation
|