Systems and Means of Informatics
2019, Volume 29, Issue 1, pp 63-73
A WAY TO ENHANCE THROUGHPUT OF PACKET SWITCHES BUILT ON THE BASIS OF INTEGRATED NETWORK PROCESSORS
Abstract
Permanent perfection and complication of protocols related to quality of service and network security forces packet switches' creators to shift their preferences from the hardware packet forwarding to soft switching methods and, implementing these methods, to programmable devices with additional network functionality. From this standpoint, network processors represent practically ready to use inexpensive programmable switches realizing the concept of switching on shared memory. Alongside with many merits, this concept has an intrinsic throughput limitation resulting from the memory sharing itself.
A subsystem for buffering network frames and packets, which could be integrated into a network processor, removes this limitation and enables the latter to implement easily a programmable switch with an essentially higher potential throughput and all merits of switching on shared memory preserved.
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[+] About this article
Title
A WAY TO ENHANCE THROUGHPUT OF PACKET SWITCHES BUILT ON THE BASIS OF INTEGRATED NETWORK PROCESSORS
Journal
Systems and Means of Informatics
Volume 29, Issue 1, pp 63-73
Cover Date
2019-03-30
DOI
10.14357/08696527190106
Print ISSN
0869-6527
Publisher
Institute of Informatics Problems, Russian Academy of Sciences
Additional Links
Key words
buffering; integrated network processor; packet switching; switching on shared memory
Authors
V. B. Egorov 
Author Affiliations
Institute of Informatics Problems, Federal Research Center "Computer Science
and Control", Russian Academy of Sciences, 44-2 Vavilov Str., Moscow 119333, Russian Federation
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