Systems and Means of Informatics
2017, Volume 27, Issue 1, pp 108-121
A METHOD OF PACKET PROCESSING IN INTEGRATED NETWORK PROCESSORS
Abstract
The article introduces a method of packet processing in integrated network processors with conventional core architectures. Packets are processed in an internal "virtual" pipeline, with available hardware resources being its stages.
The classifier determines the route of a specific packet, and the latter follows the route under control of an assigned resource - the queue manager. In addition to general pipeline control, the manager resolves access contentions to hardware resources and provides packets with quality of service. Interaction between the queue manager and hardware resources involved into the internal pipeline is carried out uniformly through composite queues of buffer, frame, and packet descriptors. Bodies of the composite queues are arranged in a system memory while their heads or tails (depends on the queue direction) are implemented as hardware FIFO (First-In/First-Out) aligning processing rates of the queue manager and managed hardware resources of the internal pipeline.
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[+] About this article
Title
A METHOD OF PACKET PROCESSING IN INTEGRATED NETWORK PROCESSORS
Journal
Systems and Means of Informatics
Volume 27, Issue 1, pp 108-121
Cover Date
2017-03-30
DOI
10.14357/08696527170108
Print ISSN
0869-6527
Publisher
Institute of Informatics Problems, Russian Academy of Sciences
Additional Links
Key words
descriptor queue; integrated network processor; packet processing; queue manager; virtual pipeline
Authors
V. B. Egorov 
Author Affiliations
Institute of Informatics Problems, Federal Research Center "Computer Science
and Control", Russian Academy of Sciences, 44-2 Vavilov Str., Moscow 119333, Russian Federation
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