Systems and Means of Informatics
2016, Volume 26, Issue 2, pp 23-42
SELF-TIMING ANALYSIS OF ELECTRONIC CIRCUITS ON THE LOWER LEVEL OF HIERARCHY
Abstract
Self-timed circuits (independent on element's delay) have the unique properties of a lack of competitions and safe on Out-Stack-At-Fault (OSAF).
They require analysis on self-timing. In the traditional approach - analyzing of elements switching, computational complexity is so great that it does not allow analyzing the most practical circuits. The functional hierarchical method, previously proposed by the author, analyzes logic equations only at the lower level, and at the upper levels, it examines only the relationships between blocks.
The suggested method makes it possible to analyze circuits of any size effectively.
This article describes in detail this method at the lower level of the hierarchy.
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[+] About this article
Title
SELF-TIMING ANALYSIS OF ELECTRONIC CIRCUITS ON THE LOWER LEVEL OF HIERARCHY
Journal
Systems and Means of Informatics
Volume 26, Issue 2, pp 23-42
Cover Date
2016-05-30
DOI
10.14357/08696527160202
Print ISSN
0869-6527
Publisher
Institute of Informatics Problems, Russian Academy of Sciences
Additional Links
Key words
self-timed circuits; asynchronous circuits; self-timing analysis; hierarchical analysis
Authors
L. P. Plekhanov 
Author Affiliations
Institute of Informatics Problems, Federal Research Center "Computer Science
and Control", Russian Academy of Sciences, 44-2 Vavilov Str., Moscow 119333, Russian Federation
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