Informatics and Applications
2023, Volume 17, Issue 3, pp 39-48
OPTIMIZATION OF THE BUFFER MEMORY ALLOCATION SCHEME OF THE PACKET SWITCHING NODE
Abstract
The buffer of the packet switching node shared by several output communication lines is considered. Sharing buffer memory by multiple users reduces the amount of memory needed to meet latency requirements and the likelihood of packet loss. However, there is a problem of allocating buffer memory between different users, since individual users, having occupied all the memory, can restrict (or close) access to communication lines to other users which can significantly reduce the performance of the switching node as a whole. There are many different buffer memory allocation schemes, one of which, called SMA (Sharing with Minimum Allocation), is being investigated in this paper in order to reduce the costs associated with packet rejection and delay and the operation of the drive and communication lines. A multithreaded queuing system with parallel devices of the M/M/s/K type with a buffer shared according to the SMA scheme with a fixed number of storage locations reserved for each device is used as a model of the switching node. The mathematical formulation of the problem of optimizing the SMA scheme in terms of the volume of publicly accessible buffer locations is formulated in order to minimize system losses arising from rejection of applications, delay of applications in the queue, and operation of the buffer and devices. The theorem on the boundaries of the domain containing the point of the global optimum is proved. A number of statements are also given which are the consequences of the theorem about the point of the global optimum of the objective function for other models of the switching node and special cases of SMA.
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[+] About this article
Title
OPTIMIZATION OF THE BUFFER MEMORY ALLOCATION SCHEME OF THE PACKET SWITCHING NODE
Journal
Informatics and Applications
2023, Volume 17, Issue 3, pp 39-48
Cover Date
2023-10-10
DOI
10.14357/19922264230306
Print ISSN
1992-2264
Publisher
Institute of Informatics Problems, Russian Academy of Sciences
Additional Links
Key words
switching node; buffer memory allocation; optimization; queuing system
Authors
Ya. M. Agalarov
Author Affiliations
Federal Research Center "Computer Science and Control" of the Russian Academy of Sciences, 44-2 Vavilov Str., Moscow 119333, Russian Federation
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